This invention relates to electrical inverters and more particularly to circuits for controlling power pole switching in pulse width modulated inverters.
Pulse width modulated DC-to-AC inverters approximate sine wave outputs by switching power pole switches at a rate higher than the fundamental sine wave frequency of the AC output. In the design of pulse width modulated DC-to-AC inverters, it is desirable to switch the power stage in a manner which reduces certain harmonics to low values so as to ease the burden of filtering the output power to obtain a sinusoidal voltage wave. Fairly small errors in switching times can produce harmonic voltages many times greater than desired. This usually results in the circuit filter being made considerably larger than theoretically necessary to suppress these harmonics.
In a transistor inverter, for example, it is necessary to provide an underlap condition to prevent shoot-through during the switching operation. This means that to switch an output point from one polarity to another, there must be a delay after the conducting transistor is turned off, to be sure it is no longer conducting, before the other transistor is turned on. Many times load conditions are such that the second transistor does not conduct at all since load current is shunted through a commutating diode, thereby shortening the switching time to that of the transistor turn-off time. The transistor switching time is quite variable depending on the instantaneous load current as well as the transistor turn-off characteristic. Therefore, the prescribed switching schedule may not be met, resulting in unpredicted harmonics.
The present invention minimizes output distortion due to switching errors by predicting the switching time required for each switching point and using this prediction to adjust the starting time for each switching period so that switching is accomplished on schedule. In general, a reference waveform which is to be reproduced at the power pole output will be available to the switching control circuitry. Pulses within the reference wave are to be reproduced at the power pole output after a preselected time interval. This delayed switching schedule is accomplished by measuring the power pole switching time for a given pulse in an output cycle and subtracting the measured switching time from the preselected time interval to obtain a delay time. The switching period for the corresponding pulse in the succeeding output cycle is then initiated at a point equal to the delay time, as obtained from the previous cycle, following the appropriate reference waveform pulse. This process is repeated for each power pole output pulse. During steady-state operation, it is reasonable to expect that switching periods will be the same length at corresponding switching points in each subsequent cycle. Therefore, the power pole will switch after a preselected time interval following the reference wave pulses.
A circuit which performs the described delayed pole switching function is disclosed in my copending application, Ser. No. 355,073, filed Mar. 5, 1982, and entitled "Inverter Firing Control with Compensation for Variable Switching Delay", now U.S. Pat. No. 4,443,842. That application discloses a circuit and method for eliminating distortion in inverters caused by variability in switching delays of power poles, and is hereby incorporated by reference. Although tests of the circuit disclosed in that application confirmed the operation as described, random instabilities occurred causing momentary disturbances in the output voltage of the inverter. This invention seeks to remove the instability problem by eliminating the need for a comparator circuit and ensuring that only complete clock pulses are counted during the timing intervals.
A pole switch firing control circuit for controlling a pulse width modulated inverter constructed in accordance with this invention comprises: means for receiving a clock signal containing voltage pulses; means for generating a control signal having transition points for initiating a pole switch switching sequence in the inverter; a first counter for counting the number of clock voltage pulses which occur between a selected transition point in the control signal and the actual switching of an associated pole switch; means for storing the number of voltage pulses counted by the first counter during each pole switch switching sequence; and a second counter which is presettable to start counting at a number equal to the number of voltage pulses counted by the first counter during a preceding switching sequence, and connected to count the clock voltage pulses which occur after a preselected transition point of a reference signal until a preselected count has been reached, whereupon the second counter produces a carry output signal which causes the means for producing a control signal to create a second transition point in the control signal to initiate a second pole switch switching sequence in the inverter.
By appropriately timing the switching function, multiple phase inverters can be controlled by a single control circuit. The means for storing the number of voltage pulses counted by the first counter may be a shift register, which stores the count of the first counter during each switching sequence and delivers the appropriate stored count to the presettable counter at an appropriate time to produce the desired inverter output waveform.
The circuit of this invention controls the switching of a power pole switch in a pulse width modulated inverter in accordance with a method comprising the steps of: counting a series of clock pulses, which occur between a preselected transition point in a control signal and the actual switching of a power pole switch in response to the transition point, with a first counter; presetting a second counter at a count equal to the number of clock pulses counted by the first counter; operating the second counter to count clock pulses, beginning at the preset count, when a preselected transition point occurs in a reference signal; and causing a second transition point in the control signal to occur when the second counter reaches a predetermined count, thereby initiating a switching sequence in the power pole switch.